NWPGCL Assistant Manager(ICT) Exam: 2020 (DPI)প্রশ্ন ও সমাধান

Node: any active device connected to a network capable of sending, receiving, or forwarding data — computers, printers, switches, and servers are all nodes, each identified by an address (IP or MAC).

Backbone: the high-capacity central connection that links multiple smaller networks (LANs, subnetworks) together, carrying the bulk of aggregated traffic between them — much like a highway connects local roads. Interconnecting LANs across a large area over a backbone forms a WAN or MAN.

Router: a Layer-3 device that forwards packets between different networks based on IP addresses, using a routing table to choose the best path toward the destination.

Gateway: a device (often a router, firewall, or server) that connects two networks using different protocols/architectures — it translates between the two environments so they can communicate, not just directs traffic.

How they relate:

graph LR
N1[Node: PC] --- SW[Switch]
N2[Node: Printer] --- SW
SW --- R[Router]
R --- BB[Backbone]
BB --- GW[Gateway]
GW --- Internet((Internet))

Key distinction — Router vs Gateway: a router simply forwards IP packets between networks running the same protocol stack; a gateway is needed when the two sides use different protocols or address schemes and require translation — every gateway can act as a router, but not every router performs protocol translation.

Exam takeaway: Node = any network-attached device; Backbone = the main trunk connecting sub-networks; Router = path-selection based on IP; Gateway = protocol translation between dissimilar networks.

NAND and NOR are universal gates — CMOS naturally implements NAND/NOR more efficiently than AND/OR directly, because a NAND or NOR gate is built from a single stage of pull-up/pull-down MOSFET networks, while AND/OR need an extra inverter stage after that same network.

Realizing AND from NAND: AND = NOT(NAND) — add an inverter (a NAND with both inputs tied together) after a NAND gate.

graph LR
A --> N1{NAND}
B --> N1
N1 --> N2{"NAND tied = NOT"}
N2 --> Y1((AND Output))

Y = ((A·B)')' = A·B

Realizing OR from NOR: OR = NOT(NOR) — same idea, an inverter after a NOR gate.

graph LR
A --> R1{NOR}
B --> R1
R1 --> R2{"NAND tied = NOT"}
R2 --> Y2((OR Output))

Y = ((A+B)')' = A+B

Truth table verification (AND from NAND):

A	B	NAND=(AB)'	NOT(NAND)=AB
0	0	1	0
0	1	1	0
1	0	1	0
1	1	0	1

Why CMOS uses this approach: a CMOS NAND gate is built from two PMOS (pull-up, parallel) and two NMOS (pull-down, series) transistors — this arrangement directly and efficiently produces the inverted AND function; producing plain AND directly would need an additional inverter stage anyway, so designers build NAND (or NOR) as the primitive and add inversion only when the non-inverted function is actually needed.

Exam takeaway: AND = double-inverted NAND; OR = double-inverted NOR — this is also exactly how NAND/NOR universality is proven, since every basic gate can be built from NAND alone (or NOR alone).