Introduction
Pipelining is the single most important idea that made modern CPUs fast. Instead of finishing one instruction completely before starting the next, a pipelined processor overlaps the execution of many instructions at once — the way a car assembly line has many cars in progress at different stations. This overlap does not make one instruction finish faster, but it dramatically increases throughput (instructions completed per unit time).
But overlapping creates problems. When one instruction needs a result that an earlier, still-unfinished instruction has not produced yet, or when a branch changes which instruction should run next, the pipeline can produce wrong answers if left unchecked. These problem situations are called hazards. Understanding pipelining and the three classes of hazards — structural, data, and control — is a very high-yield topic in BCS, Bank IT, and IT-officer exams. Questions typically test the classic 5-stage pipeline, speedup formulas, and how each hazard is caused and resolved.
Learning Objectives
- Explain what pipelining is and why it increases throughput without reducing single-instruction latency.
- Name and describe the classic 5-stage RISC pipeline (IF, ID, EX, MEM, WB).
- Define and compute pipeline speedup, ideal CPI, and the effect of stalls.
- Distinguish the three hazard types: structural, data, and control.
- Identify RAW, WAR, and WAW data dependences and know which occur in a simple in-order pipeline.
- Apply forwarding (bypassing), stalling (bubbles), and branch techniques to resolve hazards.
- Solve numeric exam problems on pipeline timing and speedup.