Combined Bank Assistant Programmer — Exam: 09.06.2023প্রশ্ন ও সমাধান
- Set by
- Combined Bank
- Post
- Assistant Programmer
- Exam date
- 9 Jun 2023
- Questions
- 8 (0 MCQ, 8 written)
- Exam guide
- Bank IT jobs · ব্যাংকের আইটি চাকরি
- Cyber Security · সাইবার নিরাপত্তা 2
- Data Structures · ডেটা স্ট্রাকচার 1
- Database · ডেটাবেজ 1
- Digital Logic · ডিজিটাল লজিক 1
- Networking · নেটওয়ার্কিং 1
- Operating Systems · অপারেটিং সিস্টেম 1
- Software Engineering · সফটওয়্যার ইঞ্জিনিয়ারিং 1
Given the following values, compute function point when all complexity adjustment factor (CAF) and weighting factors are average.
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Consider page reference string 1, 3, 0, 3, 5, 6, 3 with 3 page frames. Find the number of page faults.
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CRC is a redundancy error technique used to determine the error. Suppose the original data is 11100 and divisor is 1001.
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Attacker steals private key of website that uses transport layer security and remains undetected what can be done with private key?
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A & B two frames in a browser loaded from different origins. Why is it a reasonable security policy to allow A to navigate B to another origin base only on whether the display area of A contains dis-pare of B and A has the control over area.
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Problem solved more efficiently in adjacency list representation then adjacency matrix representation and problem solved more effective in adjacency matrix adjacency list.
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Suppose we have a relational database with five tables. table key Attributes S(sid, A) Sid T(tid, B) Tid U(uid, C) Uid R(sid, tid, D) sid, tid Q(tid, uid, E) tid, uid Here R implements a many-to-many relationship between the entities implemented with tables S and T, and Q implements a many-to-many relationship between the entities implemented with tables T and U.
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What is Half Adder circuit? Expalin with logic circuit.
Model answer
Direct answer. A half adder is a combinational circuit that adds two single binary digits (A, B) and produces two outputs, Sum and Carry — it has no carry-in input, which is the key difference from a full adder.
Truth table:
| A | B | Sum | Carry |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Boolean expressions (read directly from the table):
- Sum = A XOR B
- Carry = A AND B
Logic circuit:
graph LR
A((A)) --> X{XOR}
B((B)) --> X
X --> Sum[Sum]
A --> AN{AND}
B --> AN
AN --> Carry[Carry]
Why XOR gives Sum: Sum must be 1 exactly when A and B differ (0+1 or 1+0 = 1, no carry) and 0 when they're equal (0+0=0, or 1+1=0 with a carry) — this is precisely the XOR truth table.
Limitation: a half adder cannot accept a carry-in from a previous (less-significant) bit position, so it can only add the least-significant bit of a multi-bit number. Adding more bits requires a full adder (which takes A, B, and Carry-in, producing Sum and Carry-out) chained together, e.g. a ripple-carry adder.
Exam takeaway: Half adder = XOR (Sum) + AND (Carry), 2 inputs/2 outputs, no carry-in — the basic building block that full adders extend to support multi-bit addition.
Question text is from the public recruitment exam; answers and explanations are written by ARBS Academy. All past papers · Bank IT jobs guide