Civil Aviation Authority of Bangladesh (CAAB) Assistant Maintenance Engineer (AME) Exam: 2022প্রশ্ন ও সমাধান

In data communication, the transmission mode describes how the sender and receiver stay in step (timed) while bits/bytes move across the link.

Basis	Synchronous Transmission	Asynchronous Transmission
Unit sent	Large blocks/frames of data	Individual bytes/characters
Timing	Sender and receiver clocks are synchronized (shared clock or embedded sync pattern)	No shared clock; each byte is self-timed
Start/stop bits	Not used — a preamble/sync sequence marks frame boundaries	Every byte is wrapped with a start bit and one or more stop bits
Gaps	No gap between characters inside a block	Idle gaps can occur between bytes
Overhead	Low per-byte overhead	Extra overhead per byte (start/stop bits)
Speed	Faster	Slower
Cost/hardware	Costlier — needs clock recovery circuitry	Cheaper, simpler hardware
Typical use	SONET/SDH, synchronous serial links, USB	RS-232 serial ports, old modems, keyboard-to-PC links

Exam takeaway: synchronous transmission is clocked and block-oriented (fast, costly); asynchronous transmission is self-timed with start/stop bits framing every character (simple, slower, cheaper).

A logic gate is a basic electronic circuit that implements a Boolean function (AND, OR, NOT, NAND, NOR, XOR, XNOR) on one or more binary inputs to produce a single binary output.

A universal gate is one from which every other basic gate — and hence any digital circuit — can be built using only copies of that gate. NAND and NOR are each universal.

Truth tables

A	B	A NAND B	A NOR B
0	0	1	1
0	1	1	0
1	0	1	0
1	1	0	0

Proof using only NAND gates

1. NOT: tie both inputs of a NAND together: Y = (A.A)' = A'
2. AND: a NAND followed by a NOT (itself built from NAND): Y = ((A.B)')' = A.B
3. OR: invert A and B first (using NAND-as-NOT), then NAND them: Y = (A'.B')' = A + B (De Morgan's law)

Proof using only NOR gates

1. NOT: tie both inputs of a NOR together: Y = (A+A)' = A'
2. OR: a NOR followed by a NOT (built from NOR): Y = ((A+B)')' = A + B
3. AND: invert A and B first (using NOR-as-NOT), then NOR them: Y = (A'+B')' = A.B (De Morgan's law)

graph LR
 subgraph NOT_using_NAND
 A1[A] --> ND1[NAND both inputs A]
 ND1 --> Y1[Output NOT A]
 end
 subgraph AND_using_NAND
 A2[A] --> ND2[NAND]
 B2[B] --> ND2
 ND2 --> ND3[NAND both inputs tied]
 ND3 --> Y2[Output A AND B]
 end
 subgraph OR_using_NAND
 A3[A] --> ND4[NAND both inputs A]
 B3[B] --> ND5[NAND both inputs B]
 ND4 --> ND6[NAND]
 ND5 --> ND6
 ND6 --> Y3[Output A OR B]
 end

Exam takeaway: since NOT, AND and OR (the functionally complete set) can each be built from NAND alone (or NOR alone), NAND and NOR are called universal gates — this is why real chips are often built almost entirely from NAND gates.