CPU Organization: ALU, Registers, Buses, Instruction Cycle and Addressing Modes · সিপিইউ সংগঠন: এএলইউ, রেজিস্টার, বাস, ইনস্ট্রাকশন সাইকেল ও অ্যাড্রেসিং মোড

1. What the CPU is and its three main parts

A program is a list of machine instructions stored in memory. The CPU (also called the processor) reads those instructions one by one and carries them out. Inside it there are three main parts:

Part	Full name	What it does	What it does not do
ALU	Arithmetic Logic Unit	Arithmetic (add, subtract, compare, often multiply and divide) and logic (AND, OR, NOT, XOR, shifts); sets the status flags	It does not decide which instruction runs next
CU	Control Unit	Fetches and decodes instructions and sends timed control signals to the ALU, registers, memory and I/O	It does not calculate or store data
Registers	–	Tiny, very fast storage cells inside the CPU that hold the instruction, addresses, operands and results being used right now	They are not main memory (only a few dozen exist)

The CPU, the main memory and the input/output (I/O) devices together make up the basic computer system, joined by the system bus. Modern CPUs also contain cache memory on the same chip, but exams still list the main components of a CPU as ALU, CU and registers, so "cache" is the usual answer to "which is not a main component of the CPU?".

2. The registers you must know

Register	Full name	What it holds
PC	Program Counter (also called the Sequence Control Register or instruction pointer, IP, on Intel x86)	The address of the next instruction to fetch
IR	Instruction Register	The current instruction, just fetched from memory
MAR	Memory Address Register	The address of the memory location to read or write; it drives the address bus
MDR / MBR	Memory Data (Buffer) Register	The data just read from memory or about to be written; it sits on the data bus
AC	Accumulator	One operand and the result of an ALU operation (in accumulator-based CPUs the ALU puts its result here)
SP	Stack Pointer	The address of the top of the stack (used by PUSH, POP, CALL and RET)
Flags / PSW	Status register (Program Status Word)	One-bit results of the last operation: Zero, Carry, Sign, Overflow, Parity, and the interrupt-enable bit
GPRs	General-purpose registers (R0, R1 … or AX, BX … on x86)	Operands, addresses and temporary values chosen by the program
Index register	–	An offset added to an address (used for arrays, section 6)

Two pairs cause most mistakes:

• PC vs IR: PC holds an address (where the next instruction is); IR holds the instruction itself.
• MAR vs MDR: MAR holds an address (which cell); MDR holds the contents (what is in that cell).

Flags example (a written question): after an operation whose result is zero, the Zero flag (ZF) = 1. On Intel x86 the Parity flag (PF) = 1 when the low byte of the result has an even number of 1-bits, so a result with an even count of 1s sets PF (a zero result also sets PF, because zero 1-bits is even). The Sign flag copies the result's top bit, and the Carry flag records a carry or borrow out of the top bit.

3. Buses and how much memory a CPU can address

The system bus is a set of parallel wires with three groups:

Bus	Carries	Direction	Its width decides
Address bus	The memory or I/O address the CPU wants	One way: CPU → memory/I/O	How many locations can be addressed
Data bus	The instruction or data being moved	Both ways	How many bits move in one transfer
Control bus	Read, write, clock, interrupt request and acknowledge, bus request	Individual lines go either way	The timing and type of each transfer

The rule: with n address lines the CPU can name 2ⁿ different locations. If memory is byte-addressable (one address per byte, the usual case), that is 2ⁿ bytes.

Worked example 1: address lines → memory size.

Address lines	Locations 2ⁿ	Memory (byte-addressable)	Example
16	65,536	64 KiB	Intel 8085
20	1,048,576	1 MiB	Intel 8086
32	4,294,967,296	4 GiB	32-bit CPUs (without extensions)
64	18,446,744,073,709,551,616	16 EiB	Theoretical limit of a 64-bit address

Step by step for 20 lines: 2²⁰ = 2¹⁰ × 2¹⁰ = 1,024 × 1,024 = 1,048,576 bytes = 1 MiB (exams write "1 MB").

32-bit vs 64-bit processors. The "bit" number is the width of the general registers and the natural word the ALU handles. A 32-bit address reaches at most 2³² bytes = 4 GB. A 64-bit address could in theory reach 2⁶⁴ bytes = 16 EB (exabytes), which is the usual answer to "maximum memory of a 64-bit processor". Real x86-64 chips implement fewer address bits (48-bit virtual addresses = 256 TiB, or 57-bit with five-level paging), and the operating system sets its own lower limit. A 64-bit CPU also handles bigger integers in one step and has more registers.

Intel 8086 physical address (asked in written papers). The 8086 has 16-bit registers but a 20-bit address bus, so it combines a segment and an offset: physical address = segment × 16 + offset (shift the segment left by one hex digit, then add). With CS = 4000h and IP = 9F20h: 40000h + 9F20h = 49F20h.

4. The instruction cycle: fetch, decode, execute

The CPU runs the same loop for every instruction, from power-on to shut-down. On power-on the PC is loaded with a fixed start address, so the very first instructions come from the firmware (ROM BIOS or UEFI), not from the disk.

The fetch step in register-transfer form (each line is one clock step):

1. MAR ← PC (the address of the next instruction goes to the address bus)
2. MDR ← Memory[MAR], and at the same time PC ← PC + 1
3. IR ← MDR (the instruction is now in the instruction register)

"PC + 1" assumes each instruction fills one memory word. On byte-addressed machines the PC moves on by the instruction's length in bytes, for example + 4 for 32-bit RISC instructions.

So the register loaded with the contents of the memory location pointed to by the PC is the IR (via the MDR), and the PC already points to the following instruction while the current one runs.

Three time units are often confused: a clock cycle is one tick of the clock (period = 1 ÷ frequency); a machine cycle is one memory or I/O access (several clock cycles); an instruction cycle is everything needed for one instruction (one or more machine cycles).

5. Instruction formats

An instruction has an opcode (the operation: ADD, LOAD, JUMP) and zero or more operands (the data, or where to find it). Instruction sets are classified by how many addresses an instruction carries. Computing X = (A + B) × (C + D):

Format	Example	Meaning	Instructions needed for X
3-address	ADD T1, A, B	T1 ← A + B	3 (ADD, ADD, MUL)
2-address	ADD A, B	A ← A + B	5 (MOV T1, A; ADD T1, B; MOV X, C; ADD X, D; MUL X, T1); the common register version (MOV R1, A; ADD R1, B; MOV R2, C; ADD R2, D; MUL R1, R2; MOV X, R1) takes 6, the count most keys use
1-address	ADD B	AC ← AC + B (the accumulator is implied)	7 (LOAD, ADD, STORE, LOAD, ADD, MUL, STORE)
0-address	ADD	Pop two values, push their sum (stack machine)	8 (PUSH A, PUSH B, ADD, PUSH C, PUSH D, ADD, MUL, POP X)

Fewer addresses make each instruction shorter but the program longer.

Field sizes: a field of k bits can hold 2ᵏ different values. A 16-bit instruction with a 4-bit opcode and a 12-bit address field can encode 2⁴ = 16 operations and reach 2¹² = 4,096 addresses directly.

6. Addressing modes

The addressing mode tells the CPU how to find the operand. The address it ends up with is the effective address (EA). Below, A is the address or constant field of the instruction and (R) means "the contents of register R".

Mode	Rule	Example	Result of the example	Memory reads for the operand	Typical use
Immediate	Operand = A	MOV R1, #5	R1 = 5	0	Constants
Direct (absolute)	EA = A	LOAD R1, 500	R1 = M[500]	1	Fixed variables
Indirect	EA = M[A]	LOAD R1, @500 with M[500] = 800	R1 = M[800]	2	Pointers in memory
Register	Operand = (R)	ADD R1, R2	R1 = R1 + R2	0	Fast arithmetic
Register-indirect	EA = (R)	LOAD R1, (R2) with R2 = 800	R1 = M[800]	1	Pointers in registers
Indexed	EA = A + (X)	LOAD R1, 1000(X) with X = 24	R1 = M[1024]	1	Arrays
Relative (PC-relative)	EA = (PC) + A	JMP +20 with PC = 301	Jumps to 321	1 (for data); a jump just loads PC	Branches, position-independent code

Also named in exams: implied (the operand is fixed by the opcode, e.g. "complement the accumulator"), base-register (EA = base register + displacement, used for relocation; the same sum as indexed but a different purpose) and auto-increment/decrement (register-indirect that then steps the register; natural for stacks).

Worked example 2: effective addresses. Memory holds M[500] = 800, M[800] = 42 and M[524] = 77. Register R2 = 800, index register X = 24, and the address field is A = 500.

1. Immediate #500: the operand is 500 itself; no memory read.
2. Direct 500: EA = 500, operand = M[500] = 800.
3. Indirect @500: EA = M[500] = 800, operand = M[800] = 42 (two memory reads).
4. Register-indirect (R2): EA = 800, operand = 42 (one read, because the pointer was already in a register).
5. Indexed 500(X): EA = 500 + 24 = 524, operand = M[524] = 77.

7. RISC vs CISC, and von Neumann vs Harvard

Point	CISC	RISC
Full form	Complex Instruction Set Computer	Reduced Instruction Set Computer
Instructions	Many, some doing multi-step work	Fewer, simple
Length	Variable	Fixed (for example 32 bits)
Cycles per instruction	Several, varies	About one, made possible by pipelining
Memory access	Many instructions can use memory operands	Only LOAD and STORE touch memory (load/store design)
Addressing modes	Many	Few
Registers	Fewer	Many
Control unit	Usually microprogrammed	Usually hardwired
Code size	Smaller	Larger
Examples	Intel and AMD x86 (x86-64)	ARM, RISC-V, MIPS, SPARC, PowerPC

Most smartphones use ARM processors, which are RISC, chosen for low power. Exam keys say a RISC processor is faster at the same clock, because its simple instructions finish in about one cycle each. (Modern x86 chips translate their CISC instructions into RISC-like micro-operations inside, so in real chips the gap has narrowed.)

Point	Von Neumann	Harvard
Memory	One memory holds both instructions and data (the stored-program idea, 1945)	Separate memories for instructions and data
Buses	One set shared by both	Separate buses for each
Fetch instruction and data together?	No: they take turns (the von Neumann bottleneck)	Yes, in the same cycle
Cost and design	Simpler, cheaper, flexible use of memory	More hardware, faster for the same clock
Where used	General-purpose computers (at the programmer's level)	Microcontrollers (for example AVR, PIC) and DSPs

Today's PC and phone processors are a modified Harvard design: separate level-1 instruction and data caches inside the chip, but one shared main memory, so programs still see a von Neumann machine.

8. Clock speed, CPI, MIPS and CPU time

• Clock rate (frequency) f, in hertz: 2.40 GHz means 2.4 × 10⁹ clock ticks per second. Clock period = 1 ÷ f (0.5 ns at 2 GHz).
• CPI (cycles per instruction): the average number of clock cycles an instruction needs.
• CPU time = instruction count × CPI ÷ f (or × CPI × clock period).
• MIPS (million instructions per second) = f ÷ (CPI × 10⁶).

Worked example 3 (MCQ): 10⁹ instructions, CPI = 2, clock = 1 GHz. CPU time = 10⁹ × 2 ÷ 10⁹ = 2 s.

Worked example 4: an instruction mix. A 700 MHz CPU runs three instruction types needing 4, 8 and 10 clock cycles, making up 30%, 60% and 10% of the instructions. Find the MIPS rate.

1. Average CPI = 0.30 × 4 + 0.60 × 8 + 0.10 × 10 = 1.2 + 4.8 + 1.0 = 7.
2. MIPS = 700 × 10⁶ ÷ (7 × 10⁶) = 100 MIPS.

The same calculation in Python (this exact code was run to check the answer):

clock_hz = 700e6
mix = [(4, 0.30), (8, 0.60), (10, 0.10)]   # (clock cycles, share of instructions)

cpi = sum(cycles * share for cycles, share in mix)
mips = clock_hz / (cpi * 1e6)
time_s = 1e9 * cpi / clock_hz              # time for one billion instructions

print(f"CPI  = {cpi:.1f}")
print(f"MIPS = {mips:.0f}")
print(f"Time for one billion instructions = {time_s:.0f} s")

Output:

CPI  = 7.0
MIPS = 100
Time for one billion instructions = 10 s

Worked example 5: a faster clock is not always faster. Computer A runs at 3.2 GHz with CPI 2.0; computer B runs at 2.4 GHz with CPI 1.2 on the same program.

1. A completes 3.2 × 10⁹ ÷ 2.0 = 1.6 × 10⁹ instructions per second.
2. B completes 2.4 × 10⁹ ÷ 1.2 = 2.0 × 10⁹ instructions per second.
3. B is faster, by 2.0 ÷ 1.6 = 1.25 times, even though its clock is slower.

Another written question in the same style: 10⁹ instructions at 2 GHz, where 50% take 3 cycles, 30% take 4 and 20% take 5. CPI = 1.5 + 1.2 + 1.0 = 3.7, so time = 10⁹ × 3.7 ÷ (2 × 10⁹) = 1.85 s.

Other things that make a CPU faster: more cores, a bigger and faster cache, a wider word and data bus, pipelining and executing several instructions per cycle.

9. Pipelining, superscalar, multicore and hyper-threading

Pipelining overlaps instructions like an assembly line: while one instruction executes, the next is decoded and a third is fetched. The classic five stages (used by the MIPS and DLX teaching designs) are:

1. IF: instruction fetch
2. ID: instruction decode and register read
3. EX: execute (ALU operation or address calculation)
4. MEM: memory access (load or store)
5. WB: write back the result to a register

Clock cycle	1	2	3	4	5	6	7
Instruction 1	IF	ID	EX	MEM	WB
Instruction 2		IF	ID	EX	MEM	WB
Instruction 3			IF	ID	EX	MEM	WB

With k stages and n instructions (one cycle per stage, no stalls): without a pipeline it takes n × k cycles; with one it takes k + n − 1. Prefetched instructions wait in a FIFO queue (first in, first out).

Worked example 6: 100 instructions on a 5-stage pipeline: 5 + 100 − 1 = 104 cycles instead of 100 × 5 = 500, a speed-up of 500 ÷ 104 ≈ 4.81 (it approaches 5, the number of stages, for long programs).

Hazards stop the pipeline from finishing one instruction every cycle:

• Structural hazard: two stages need the same hardware at once (for example one memory port for both IF and MEM).
• Data hazard: an instruction needs a result that an earlier one has not written yet. In ADD R1, R2, R3 followed by SUB R4, R1, R5, the SUB needs R1 before the ADD's write-back. It is solved by forwarding (bypassing) the result or by stalling.
• Control hazard: after a branch the CPU does not yet know which instruction comes next; branch prediction guesses.

Related terms: a superscalar CPU issues more than one instruction per clock using several pipelines (the original Pentium had two, called U and V). A multicore chip has several complete cores; homogeneous multicore uses identical cores, heterogeneous mixes types (for example ARM big.LITTLE, or Intel performance and efficiency cores). Hyper-threading is Intel's name for simultaneous multithreading: one physical core keeps the state of two threads and can issue instructions from both in the same clock cycle, so "2 cores, 4 threads" means two physical cores each running two hardware threads. It uses idle parts of the core and typically helps multitasking, but it is not the same as doubling the cores.

Cache memory in brief: a hit means the data is found in the cache; a miss means the CPU must fetch it from main memory. Average access time = hit rate × hit time + miss rate × miss time. With an 80% hit rate, 5 ns per hit and 50 ns per miss: 0.8 × 5 + 0.2 × 50 = 4 + 10 = 14 ns. This assumes the cache and main memory are searched at the same time. If memory is tried only after the cache misses (hierarchical access), every access pays the hit time first: average = hit time + miss rate × miss penalty = 5 + 0.2 × 50 = 15 ns. Use the method the question implies; most MCQ keys use the first.

10. Related terms: Flynn's classes, control-unit design, I/O methods and byte order

Flynn's taxonomy sorts computers by how many instruction streams and data streams run at once:

Class	Meaning	Example
SISD	Single instruction, single data	A classic single-core processor
SIMD	One instruction applied to many data items together	Vector units (SSE, AVX), GPUs, array processors
MISD	Several instructions on the same data	Rare; a few fault-tolerant designs
MIMD	Several processors, each with its own instructions and data	Multicore chips, clusters

Hardwired vs microprogrammed control unit:

Point	Hardwired	Microprogrammed
How control signals are made	Fixed logic circuits (gates, decoders, flip-flops)	Read from microinstructions stored in a control memory (control store)
Speed	Faster	Slower (each step reads the control memory)
Changing or adding instructions	Hard: the circuit must be redesigned	Easy: rewrite the microprogram
Usual in	RISC	CISC

Three ways to do I/O:

• Polling (programmed I/O): the CPU keeps checking a device's status register until it is ready, which wastes CPU time.
• Interrupt-driven I/O: the device signals the CPU when it is ready; the CPU saves the PC and flags, runs the interrupt service routine, then resumes.
• DMA (direct memory access): a DMA controller moves a whole block between the device and memory over the bus without the CPU copying each word; the CPU only sets up the transfer and gets one interrupt when it ends. Best for fast devices such as disks.

Byte order (endianness) is the order in which the bytes of a multi-byte value are stored. Storing 12345678h from a starting address: little-endian puts the lowest byte first (78 56 34 12; Intel x86), big-endian puts the highest byte first (12 34 56 78; network byte order).

11. Tricky exam cases

• "Which is not a main component of the CPU?" Cache. The three main parts are ALU, CU and registers.
• Relative addressing with the PC: "PC = 825, address field = 24, relative mode, when the instruction is read from memory". During the fetch the PC is incremented to 826, so EA = 826 + 24 = 850, not 849. Always add to the updated PC.
• Logical shift: ABCD hex shifted right by two bits (zeros enter from the left) → 1010 1011 1100 1101 becomes 0010 1010 1111 0011 = 2AF3.
• Fastest operation: the keyed answer is a bitwise OR (or AND, XOR), because each bit is computed on its own with no carry to pass along, while addition needs a carry chain. On modern CPUs OR and ADD both usually take one cycle; multiplication takes several and division the most.
• Largest 32-bit signed integer: 2³¹ − 1 = 2,147,483,647 (one bit is the sign). In C the size of int is implementation-defined; the C standard only promises at least 16 bits, though it is 32 bits on all common desktop compilers.
• Physical connection between processor, memory and other parts: the system bus; the bus used to send an address, the address bus (the only one-way bus).
• Microprocessors (a whole CPU on one chip, starting with the Intel 4004 in 1971) mark the fourth generation of computers.
• Not every core count is "cores × 2 threads": the Core i7-9700K has 8 cores and 8 threads (no hyper-threading), while the i7-8700K has 6 cores and 12 threads. Check the vendor's data sheet rather than assuming.