47th BCS Technicalপ্রশ্ন ও সমাধান
- Set by
- BCS
- Questions
- 8 (0 MCQ, 8 written)
- Exam guide
- BCS (ICT and CSE cadre) · বিসিএস (আইসিটি ও সিএসই ক্যাডার)
- Data Structures · ডেটা স্ট্রাকচার 2
- Computer Architecture · কম্পিউটার আর্কিটেকচার 1
- Digital Logic · ডিজিটাল লজিক 1
- General ICT · সাধারণ আইসিটি 1
- Mathematics · গণিত 1
- Networking · নেটওয়ার্কিং 1
- Programming · প্রোগ্রামিং 1
(a) Explain Thevenin's theorem. Describe the steps required to find the Thevenin equivalent voltage and resistance of a given linear circuit.
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(a) Define Boolean algebra. State its fundamental laws and illustrate how these laws are applied to simplify logic expressions.
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(a) What are the differences between Harvard and Von Neumann architecture? Explain using a suitable diagram.
Model answer
| Feature | Von Neumann Architecture | Harvard Architecture |
|---|---|---|
| Memory | Single shared memory for instructions and data | Separate physical memories for instructions and data |
| Bus | One common bus for both instructions and data | Separate instruction bus and data bus |
| Instruction execution | Needs multiple cycles (fetch then execute share the bus) | Can fetch instruction and access data in the same cycle |
| Simultaneous access | Not possible (bus is a bottleneck — the "Von Neumann bottleneck") | Possible, since paths are independent |
| Cost/complexity | Simpler, cheaper | More complex, costlier |
| Typical use | General-purpose PCs, laptops, servers | Microcontrollers, DSPs, embedded/signal-processing chips |
graph TD
subgraph VonNeumann["Von Neumann Architecture"]
M[(Shared Memory\nInstructions + Data)] <--> BUS[Common Bus] <--> CPU1[CPU: ALU + Control Unit]
end
subgraph Harvard["Harvard Architecture"]
IM[(Instruction Memory)] <--> IB[Instruction Bus] <--> CPU2[CPU: ALU + Control Unit]
DM[(Data Memory)] <--> DB[Data Bus] <--> CPU2
end
Exam takeaway: Von Neumann's single shared bus is simple but creates the "fetch vs access" bottleneck; Harvard's dual-bus design removes that bottleneck at the cost of extra hardware, which is why it dominates in performance-critical embedded/DSP chips.
(a) Explain the concept of Entropy in information theory. How does it quantify the uncertainty of a random message source?
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(a) Define constructor, destructor, and copy constructor in object-oriented programming context.
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(a) Define a graph and explain the concepts of degree, path, cycle, and connectedness in an undirected graph: Differentiate between Eulerian and Hamiltonian graphs with examples.
Model answer
A graph G = (V, E) is a set of vertices V connected by a set of edges E; in an undirected graph each edge {u, v} has no direction.
- Degree of a vertex = number of edges incident to it.
- Path = a sequence of distinct vertices where consecutive ones are connected by an edge.
- Cycle = a path that starts and ends at the same vertex, with no repeated edges/vertices in between.
- Connectedness = a graph is connected if there exists a path between every pair of vertices.
Eulerian vs Hamiltonian graphs
| Aspect | Eulerian Graph | Hamiltonian Graph |
|---|---|---|
| Definition | Contains a closed walk that uses every edge exactly once | Contains a cycle that visits every vertex exactly once |
| Existence condition | Connected graph where every vertex has even degree | No simple general condition (NP-complete to decide) |
| Focus | Edge-covering | Vertex-covering |
| Classic example | K4 is not Eulerian (odd-degree vertices); a cycle graph Cₙ is Eulerian | K4 (complete graph on 4 vertices) is Hamiltonian |
graph LR
A((A)) --- B((B))
B --- C((C))
C --- D((D))
D --- A
A --- C
The graph above (a 4-cycle plus one diagonal A-C) has vertices of degree 3,2,3,2 — since A and C are odd-degree, it is not Eulerian, but a Hamiltonian cycle A→B→C→D→A visiting every vertex once does exist, so it is Hamiltonian.
Exam takeaway: Eulerian-ness is easy to check (even degree + connected) and solvable in polynomial time; Hamiltonian-ness has no such shortcut and is NP-complete in general — the two properties are independent of each other.
(a) Explain the differences between stack and queue data structures in terms of their operations, memory organization and real-life applications. Provide one example use-case for each.
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(a) Explain the concept of congestion control in computer networks. Discuss briefly how TCP manages congestion during data transmission.
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Question text is from the public recruitment exam; answers and explanations are written by ARBS Academy. All past papers · BCS (ICT and CSE cadre) guide