Bangladesh Bank Assistant Maintenance Engineer Exam 2019 — Question Solution | বাংলাদেশ ব্যাংক সহকারী রক্ষণাবেক্ষণ প্রকৌশলী নিয়োগ পরীক্ষা ২০১৯ — প্রশ্ন সমাধান

Node
A node is any addressable device attached to a network that can send, receive or forward data. End nodes (hosts) such as PCs, servers, printers and IP phones create or consume data; intermediate nodes such as switches, routers, modems and access points pass data on. End nodes and managed devices are identified by a hardware (MAC) address on a LAN and by a logical IP address on an IP network; a simple unmanaged switch or hub forwards data without an address of its own.

Backbone
The backbone is the high-capacity core of a network that interconnects smaller networks (LANs, subnets, buildings) and carries their combined traffic. It uses the fastest links and devices, usually optical fibre at 10/40/100 Gbps with core switches or routers. In a distributed backbone several core devices are spread over the site; in a collapsed backbone all LANs meet at one core switch/router. When LANs across a city or a country are joined over a backbone, the result is a MAN or a WAN; the Internet backbone is made of large carriers' long-haul fibre and submarine cables.

Router
A router is a Layer-3 (Network layer) device that connects different IP networks and forwards each packet towards its destination by looking up the destination IP address in its routing table (built statically or by routing protocols such as OSPF or BGP). Each interface belongs to a different network, so a router separates broadcast domains; it can also perform NAT, ACL filtering and DHCP.

Gateway
A gateway is the entry/exit point between two networks. In the strict sense it translates between networks that use different protocols or architectures, and it can work at any layer up to Layer 7 — for example a VoIP gateway converting SIP calls to the telephone network, an email gateway, or a NAT64 gateway joining IPv6 and IPv4 networks. On a host, the default gateway is the router interface (e.g. 192.168.1.1 on a 192.168.1.0/24 LAN) to which all traffic for other networks is sent.

graph LR
    N1["Node: PC"] --- SW["Access switch"]
    N2["Node: printer"] --- SW
    SW --- R1["Router: default gateway of LAN-1"]
    R1 === BB["Backbone: fibre core"]
    R2["Router of LAN-2"] === BB
    BB === GW["Gateway: edge to a different network"]
    GW --- NET(("Internet or telephone network"))

Aspect	Router	Gateway
Main job	Chooses a path and forwards packets between IP networks	Joins dissimilar networks and translates protocol/format
OSI layer	Layer 3	Any layer, often up to Layer 7
Networks joined	Same protocol (IP) on both sides	Different protocols or architectures
Example	Office router linking the LAN to the ISP	VoIP gateway: SIP ↔ telephone network

Exam tip: Node = any addressable network device; Backbone = high-speed core linking networks; Router = IP-based path selection (L3); Gateway = entry point that translates between dissimilar networks — a LAN's router is called its "default gateway" because it is the exit point for off-subnet traffic.

Direct answer: in CMOS the natural gates are NAND and NOR, because one static CMOS stage always inverts. So an AND gate is a CMOS NAND followed by a CMOS inverter, and an OR gate is a CMOS NOR followed by a CMOS inverter:

• AND: Y = ((A·B)′)′ = A·B — 4 + 2 = 6 transistors
• OR: Y = ((A + B)′)′ = A + B — 4 + 2 = 6 transistors

Why a second stage is needed: a static CMOS stage has a PMOS pull-up network (to VDD) and an NMOS pull-down network (to GND). An input of 1 turns an NMOS on and pulls the output to 0, so a single stage can only give an inverted function (NOT, NAND, NOR). The non-inverted AND/OR must add an inverter (1 PMOS + 1 NMOS, gates tied together).

1. AND = CMOS NAND + inverter

CMOS NAND: PMOS P1 (gate A) and P2 (gate B) in parallel from VDD to node X; NMOS N1 (gate A) and N2 (gate B) in series from X to GND.

graph TB
  VDD1["VDD"] --- P1["PMOS P1, gate A"]
  VDD1 --- P2["PMOS P2, gate B"]
  P1 --- X["node X = (AB)'"]
  P2 --- X
  X --- N1["NMOS N1, gate A"]
  N1 --- N2["NMOS N2, gate B"]
  N2 --- GND1["GND"]
  X --> INV1["CMOS inverter: PMOS P3 + NMOS N3"]
  INV1 --> Y1(("Y = AB"))

A	B	P1	P2	N1	N2	X = (AB)′	Y = X′
0	0	ON	ON	OFF	OFF	1	0
0	1	ON	OFF	OFF	ON	1	0
1	0	OFF	ON	ON	OFF	1	0
1	1	OFF	OFF	ON	ON	0	1

X is pulled low only when both series NMOS conduct (A = B = 1); the inverter then gives Y = AB.

2. OR = CMOS NOR + inverter

CMOS NOR: PMOS P4 (gate A) and P5 (gate B) in series from VDD to node Z; NMOS N4 (gate A) and N5 (gate B) in parallel from Z to GND.

graph TB
  VDD2["VDD"] --- P4["PMOS P4, gate A"]
  P4 --- P5["PMOS P5, gate B"]
  P5 --- Z["node Z = (A+B)'"]
  Z --- N4["NMOS N4, gate A"]
  Z --- N5["NMOS N5, gate B"]
  N4 --- GND2["GND"]
  N5 --- GND2
  Z --> INV2["CMOS inverter: PMOS P6 + NMOS N6"]
  INV2 --> Y2(("Y = A + B"))

A	B	P4	P5	N4	N5	Z = (A+B)′	Y = Z′
0	0	ON	ON	OFF	OFF	1	0
0	1	ON	OFF	OFF	ON	0	1
1	0	OFF	ON	ON	OFF	0	1
1	1	OFF	OFF	ON	ON	0	1

Z is pulled high only when both series PMOS conduct (A = B = 0); the inverter then gives Y = A + B.

Gate-level view (NAND and NOR as universal gates)

Target	Using only 2-input NAND gates	Using only 2-input NOR gates
AND	2 gates: X = NAND(A, B), Y = NAND(X, X)	3 gates: Y = NOR(NOR(A, A), NOR(B, B)) = (A′ + B′)′ = AB
OR	3 gates: Y = NAND(NAND(A, A), NAND(B, B)) = (A′B′)′ = A + B	2 gates: X = NOR(A, B), Y = NOR(X, X)

These counts are the fewest possible. A tied-input NAND (or NOR) works as the inverter, but it uses 4 transistors where a plain CMOS inverter uses 2, so the transistor-level AND/OR above (6 each) is the efficient form.

Exam tip: AND = NAND + inverter, OR = NOR + inverter, 6 transistors each; NAND is usually preferred over NOR because its series pair is NMOS (electrons are more mobile than holes), while NOR's series pair is the slower PMOS.